One type of prior nonvolatile memory is flash electrically erasable programmable read only memory (flash EEPROM, or "flash memory").
Flash memory combines erase features from prior nonvolatile memory types. Like prior electrically erasable programmable read only memory ("EEPROM"), flash memory is erased electrically without being removed from the computer system. Flash memory is also similar to erasable programmable read only memory ("EPROM") because flash memory is arranged in blocks such that the entire contents of each block must be erased at once. For an embodiment, a single flash memory array contains several individually-erasable blocks. Alternatively, a flash memory array comprises one block.
For one type of flash memory manufactured by Intel Corporation, an EPROM tunnel oxide ("ETOX") technology is used. The ETOX technology employs a single "floating gate" memory transistor to hold one bit of data. The programming of the memory transistor brings the value of the bit to a logical "0". Programming is accomplished by applying a large positive voltage to a select gate, applying a similar voltage to the drain, and grounding the source of the memory transistor. The select gate is positioned above the floating gate such that electrons are hot injected into the floating gate. Erasure of the flash memory brings the value of the bit to a logical "1". A large positive voltage is applied to the source of the memory transistor, causing electrons to be tunneled away from the floating gate.
As the memory transistor is repeatedly programmed and erased, "electron trapping" causes programming and erasure times to increase. During the programming of the transistor, electrons become trapped near the drain region, slowing electron hot injection in to the floating gate. Similarly erasure causes electrons to become trapped near the source region, making electron tunneling more difficult.
Electron trapping effects can cause programming and erasure operations to fail as the flash memory device ages. As a result, each program or erase operation is followed by a verification operation. Verification is performed by comparing the actual contents of the flash memory array with the intended program or erase value. If there is a discrepancy between the actual and intended values, the program or erase operation must be reinitiated. As the age of the flash memory array increases and electron trapping effects become more prevalent, the program or erase operation may have to be reinitiated a number of times. One type of Intel flash memory is qualified to withstand a minimum of 100,000 programming and erasure cycles before degradation or failure of programming and erasure times. This cycle lifetime is further extended to 1,000,000 cycles when flash memory devices incorporate wear-leveling algorithms that distribute data amongst flash memory blocks.
Prior flash memory devices that do not contain internal write control logic rely on the system microprocessor to sequence the flash memory through its program, erase, and verify steps. These devices have the disadvantage of placing a heavy burden on the microprocessor. However, they also have the advantage of allowing the microprocessor to control the number of times program and erase operations are reinitiated.
More recent flash memory devices developed by Intel Corporation have incorporated write state machines to help alleviate the heavy burden on the microprocessor. Upon receipt of a command from the microprocessor, the write state machine cycles the flash memory array through its program, erase, and verify steps automatically, reinitiating the program or erase steps as necessary. One drawback of these devices is that the microprocessor cannot access the flash memory array until either 1) the array verifies correctly, or 2) the write state machine "times out" after reinitiating the program or erase step a predetermined number of times. Because the time-out value is controlled internal to the flash memory device, the microprocessor has little control over the amount of wait time involved during programming and erasure.
In certain situations it is desirable for the microprocessor to be able to control the time-out value. One such situation arises when the flash memory device contains code for the microprocessor to execute. While one block of memory is being repeatedly erased and programmed, the microprocessor may need to wait to execute code out of another block. The microprocessor could decrease its wait time, and hence increase its efficiency, by setting a shorter time-out value for memory devices containing frequently-accessed code.
A controllable time-out value would also be desirable when the microprocessor needs to input large amounts of programming data to the flash memory device. Some Intel flash memory devices employ input buffers to allow data to be written to one buffer of the memory device while the flash memory array is being programmed out of a second buffer. The increased efficiency of this type of buffer arrangement is diminished by long time-out values that tie up the write state machine and cause the buffers to fill. By setting a short time-out value for a memory device that will be frequently programmed with a lot of data, the microprocessor can therefore increase the efficiency of its write cycles to the flash memory device.